1. Field of the Invention
The invention to be described in this specification relates to a shift register circuit formed on an insulating substrate with thin film transistors including channels of the same conductivity type. The invention to be described in this specification has modes as a shift register circuit, a display panel, and electronic apparatus.
2. Description of the Related Art
A low-temperature poly-silicon (LIPS) process allows circuit formation with both an NMOS thin film transistor (TFT) and a PMOS thin film transistor. Therefore, it is general to manufacture a circuit (so-called CMOS circuit) with these two kinds of thin film transistors in the low-temperature poly-silicon process.
However, the manufacturing of the CMOS circuit inevitably involves increase in the number of steps because two kinds of thin film transistors are used. This increase in the number of steps causes the lowering of the productivity and increase in the manufacturing cost.
Therefore, it is desired that, if possible, a circuit having the same functions as those of the CMOS circuit is achieved with merely thin film transistors including channels of the same conductivity type (with merely NMOS or PMOS thin film transistors) even when the poly-silicon process is used.
This kind of same-conductivity-type channel circuit can be applied also to circuit formation with amorphous silicon or an organic semiconductor.
For example, with amorphous silicon, circuits other than ones including merely NMOS thin film transistors may not be manufactured. As for the organic TFT, circuits other than ones including merely PMOS thin film transistors may not be manufactured.
Because of this background, it is desired to achieve a circuit having the same functions as those of the CMOS circuit with merely thin film transistors including channels of the same conductivity type (with merely NMOS or PMOS thin film transistors).
In this specification, attention will be paid on a shift register circuit particularly. It is obvious that the shift register circuit is a general-purpose circuit incorporated in a wide variety of circuits. Therefore, the shift register circuit is not limited to the specific application basically. However, the following description is based on the premise of application to a drive circuit for driving a display panel, for convenience.
The following description will deal with a related-art example of a shift register circuit used for an active-matrix driven organic EL (electroluminescence) panel.
FIG. 1 shows a system configuration example of an organic EL panel. In an organic EL panel 1 shown in FIG. 1, a pixel array part 3, a signal line driver 5, a first control line driver 7, and a second control line driver 9 are disposed on a panel substrate.
In the pixel array part 3, sub-pixels 11 are arranged in a matrix corresponding to the display resolution. FIGS. 2 and 3 show examples of the equivalent circuit of the sub-pixel 11. In both the circuit examples of the sub-pixel 11 shown in these diagrams, all of thin film transistors are formed of NMOS thin film transistors.
In the diagrams, N1 denotes a sampling transistor, N2 denotes a drive transistor, N3 denotes a lighting control transistor, and Cs denotes a hold capacitor. Furthermore, WSL, LSL, and PSL denote a write control line, a lighting control line, and a current supply line, respectively.
FIG. 2 corresponds to a circuit configuration in the case of employing a drive system that achieves the lighting operation and lighting-stop operation of an organic EL element OLED through the on/off-control of the lighting control transistor N3.
On the other hand, FIG. 3 corresponds to a circuit configuration in the case of employing a drive system that achieves the lighting operation and lighting-stop operation of the organic EL element OLED through potential change of the lighting control line LSL. In the configuration of FIG. 3, the lighting control line LSL functions also as the current supply line.
FIG. 4 shows a timing chart of writing of a signal potential Vsig (Data) to the sub-pixel 11 shown in FIGS. 2 and 3. FIG. 4A shows the drive waveform of a signal line DTL. The signal potential Vsig dependent on the pixel grayscale Data is supplied to the signal line DTL. The magnitude of a drive current supplied through the drive transistor N2 depends on the magnitude of the signal potential Vsig. The organic EL element OLED is a current-driven element, and larger drive current therefor provides higher luminance thereof.
FIG. 4B shows the drive waveform of the write control line WSL. During the period of the H level thereof, the sampling transistor N1 is turned on and the potential of the signal line DTL is written to the gate electrode of the drive transistor N2.
FIG. 4C shows the drive waveform of the lighting control line LSL. The lighting control line LSL is driven with binary values of the H level and the L level. By this potential switching, the lighting and lighting-stop of the organic EL element OLED are switch-controlled.
The sub-pixel 11 shown in FIG. 2 is different from that shown in FIG. 3 in the control amplitude of the lighting control line LSL. This is because it is sufficient for the lighting control line LSL to be capable of driving the lighting control transistor N3 in the circuit of FIG. 2, whereas it is necessary for the lighting control line LSL to supply the operating voltage of the drive transistor N2 and the organic EL element OLED in the circuit of FIG. 3.
As shown in FIG. 4, after the end of the writing of the signal potential Vsig, the lighting of the organic EL element OLED is achieved when the lighting control line LSL is at the H level, whereas the lighting of the organic EL element OLED is stopped when the lighting control line LSL is at the L level.
The peak luminance level can be controlled by varying the ratio (Duty) of the lighting period to the one-field period.
The lighting control line LSL (FIG. 4C) is used also for adjustment of the moving-image characteristics. For the adjustment of the moving-image characteristics, it is desired to adjust the number of times of lighting in a one-field period and the timing of the lighting period.
Therefore, it is desired for the second control line driver 9 to be capable of outputting plural kinds of pulses.
In addition, in the case of an active-matrix drive system and a general line-sequential writing system, these pulse waveforms need to be line-sequentially transferred.
That is, it is desired for this kind of control line driver to have the following two functions: the function capable of freely designing the pulse length of the control pulse; and the function capable of line-sequentially transferring the control pulse to the next stage.
In the sub-pixel 11 shown in FIGS. 2 and 3, for the above-described operation of writing the signal potential Vsig, threshold correction operation and mobility correction operation for the drive transistor N2 are carried out in some cases. FIG. 5 shows a timing chart of the sub-pixel 11 corresponding to FIG. 2. FIG. 6 shows a timing chart of the sub-pixel 11 corresponding to FIG. 3. The difference between the sub-pixel 11 shown in FIG. 2 and that shown in FIG. 3 is whether or not initialization operation and light-emission period control are separated from each other.
For the light-emission period control, operation of varying the ratio (Duty) of the light-emission period to the lighting-stop period is desired in order to adjust the peak luminance. Furthermore, for the light-emission period control, operation of changing the number of times of switching between the light-emission period and the lighting-stop period in the one-field period is desired in order to adjust the moving-image displaying characteristics. For these purposes, the circuit configuration of the second control line driver 9 is generally complex.
Therefore, the circuit configuration of FIG. 2, in which the supply line for the initialization pulse and the supply line for the lighting-period control pulse, different in the transfer timing of the output pulse, are separately provided, is advantageous in simplification of the control interface. However, as shown in FIG. 2, three control lines are desired: the write control line WSL, the lighting control line LSL, and the current supply line PSL.
In the following, the control operation of the sub-pixel 11, including the threshold correction operation, the mobility correction operation, and the light-emission period control, will be described below for the case of the pixel circuit shown in FIG. 3. Therefore, the description will be made with reference to FIG. 6.
As described above, the control operation used in the pixel circuit shown in FIG. 2 is the same as that used in the pixel circuit shown in FIG. 3 except for the separation of the initialization operation from the light-emission period control.
FIG. 6A shows the drive waveform of the write control line WSL. For example, during the period of the H level thereof, the sampling transistor N1 is turned on and the potential of the signal line DTL is written to the gate electrode of the drive transistor N2.
The first H-level period in FIG. 6 is used to correct variation in the threshold voltage Vth of the drive transistor N2.
On the other hand, the second H-level period in FIG. 6 is used to write the signal potential Vsig dependent on the pixel grayscale and correct variation in the mobility μ of the drive transistor N2.
The purpose of the inclination of the falling waveform of the pulse corresponding to the second H-level period is to set the optimum mobility correction period for all of the grayscales from the highest-luminance grayscale (highest signal potential) to the lowest-luminance grayscale (lowest signal potential).
The mobility correction refers to operation for correcting mobility difference between the drive transistor N2 having higher mobility p and the drive transistor N2 having lower mobility p, and the correction time thereof is determined depending on the length of the H-level period of the write control line WSL. As this correction period, a longer period is necessary for lower luminance (lower signal potential) in principle.
FIG. 6B shows the drive waveform of the signal line DTL. Two kinds of potentials are applied to the signal line DTL. An offset potential Vofs is used for threshold correction for the drive transistor N2. The signal potential Vsig is the potential that provides the pixel grayscale. The magnitude of the drive current supplied through the drive transistor N2 depends on the magnitude of the signal potential Vsig. The organic EL element OLED is a current-driven element, and larger drive current therefor provides higher luminance thereof.
FIG. 6C shows the drive waveform of the lighting control line LSL. The lighting control line LSL is driven with binary values of the H level and the L level. The first L-level period in FIG. 6 is used to provide an initialization period. The second L-level period in FIG. 6 is used to provide a lighting-stop period after the start of light emission.
The initialization operation is to set the gate-source voltage Vgs of the drive transistor N2 higher than the threshold voltage Vth thereof. This operation is necessary before execution of the threshold correction. Hereinafter, this operation will be referred to as the correction preparatory operation.
After the correction preparatory operation, the potential of the lighting control line LSL is switched to the H level, with the offset potential Vofs continuously applied to the gate electrode of the drive transistor N2. The operation with this potential relationship is the threshold correction operation. Upon the start of the threshold correction operation, the source potential Vs of the drive transistor N2 gradually increases. The increase in the source potential Vs stops at the timing when the gate-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth thereof.
At the end of the writing of the signal potential Vsig, the light-emission period starts and continues until the next writing period. In the light-emission period, the lighting of the organic EL element OLED is achieved when the lighting control line LSL is at the H level, whereas the lighting of the organic EL element OLED is stopped when the lighting control line LSL is at the L level. The peak luminance level can be controlled by varying the ratio of the lighting period length in the one-field period.
FIG. 6D shows the potential Vg of the gate electrode of the drive transistor N2. FIG. 6E shows the potential Vs of the source electrode of the drive transistor N2 (the potential of the anode of the organic EL element OLED).
As described above, the pulse lengths of the write control signal (FIG. 6A) and the lighting control signal (FIG. 6C) need to differ depending on the purpose of the drive operation.
For example, for the former signal, the length of the pulse for the threshold correction operation needs to be different from that of the pulse for the signal writing and mobility correction operation. For the latter signal, the length of the pulse corresponding to the period of the correction preparatory operation needs to be different from that of the pulse for the control of lighting/lighting-stop in the light-emission period.
Therefore, it is desired for each of the first control line driver 7 and the second control line driver 9 to be capable of outputting pulses of plural lengths. In addition, in the case of an active-matrix drive system and a general line-sequential writing system, these pulse waveforms need to be line-sequentially transferred. That is, it is desired for this kind of control line driver to have the following two functions: the function capable of freely designing the pulse length of the control pulse; and the function capable of line-sequentially transferring the control pulse to the next stage.
FIG. 7 shows a structure example of a shift register circuit that is suitable for use in the control line drive circuit that satisfies the above-described drive conditions. The shift register circuit shown in FIG. 7 has a configuration obtained by cascade-connecting 2N shift stages SR(1) to SR(2N). In this shift register circuit, each shift stage carries out operation of outputting a clock signal ck1 or ck2 input thereto as an output pulse o(k) to the control line of this shift stage by using, as drive pulses, the output pulses o(k−1) and o(k+1) of other shift stages at the previous and subsequent stages.
FIG. 8 shows drive pulse waveforms of the shift register circuit. The pulse waveforms of FIG. 8 correspond to the shift register circuit formed with merely NMOS thin film transistors.
FIG. 8A shows a start pulse st for driving the first shift stage, and FIG. 8B shows an end pulse ‘end’ for driving the 2N-th shift stage. FIG. 8C shows the clock signal ck1 for the even-numbered shift stages.
FIG. 8D shows the clock signal ck2 for the odd-numbered shift stages. FIG. 8E shows the output pulse o1 of the first shift stage SR(1). FIG. 8F shows the output pulse o(k−1) of the (k−1)-th shift stage SR(k−1). Similarly, FIGS. 8G to 8I show the output pulses o of the shift stages corresponding to the symbols shown in the diagram.
FIG. 9 shows an internal circuit example of the k-th shift stage SR. In the circuit of FIG. 9, all of the thin film transistors included in the shift stage SR are NMOS thin film transistors. The output stage of this shift stage SR is composed of NMOS thin film transistors N11 and N12 that are connected in series to each other between a power supply VSS and a clock input terminal ck and NMOS thin film transistors N13 to N16 that form a logic gate stage. The connecting midpoint between the thin film transistors N11 and N12 is connected to an output node ‘out.’
A complementary capacitor C1 is connected between the gate electrode of the thin film transistor N11 and the output terminal ‘out.’ This complementary capacitor C1 is a capacitor for complementing bootstrap operation, and is used if the gate capacitance of the thin film transistor N11 is insufficient. The complementary capacitor C1 is used also as a hold capacitor for a node A equivalent to the control interconnect of the thin film transistor N11.
On the other hand, a complementary capacitor C2 is connected between the gate electrode of the thin film transistor N12 and the power supply VSS. The complementary capacitor C2 serves as a hold capacitor for the potential of a node B equivalent to the control interconnect of the thin film transistor N12. The capacitance of the complementary capacitor C2 depends on the off-leakage amount of the transistor part and the holding period, and is used if the gate capacitance of the thin film transistor N12 is insufficient.
FIG. 10 shows the potential relationship among the input and output pulses, the node A, and the node B relating to the shift stage SR shown in FIG. 9. FIG. 10A shows the waveform of the drive pulse input to a first input terminal in1(k) (the output pulse out(k−1) of the previous register stage). FIG. 10B shows the waveform of the drive pulse input to a second input terminal in2 (k) (the output pulse out(k+1) of the subsequent register stage).
FIG. 10C shows the waveform of the clock signal ck. FIG. 10D shows the waveform of the potential of the node A (the gate potential of the thin film transistor N11). FIG. 10E shows the waveform of the potential of the node B (the gate potential of the thin film transistor N12). FIG. 10F shows the waveform of the output pulse that appears at the output node ‘out.’
As shown in FIG. 10, the potentials of the node A and the node B are switched in a complementary manner at each of the timing of the rising of the potential of the first input terminal in1 (k) to the H level and the timing of the rising of the potential of the second input terminal in2(k) to the H level.
This complementary operation is achieved by the function of the logic circuit composed of the thin film transistors N13 to N16.
For example, when the first input terminal in1(k) is at the H level and the second input terminal in2 (k) is at the L level, the thin film transistors N13 and N16 are in the on-state and the thin film transistors N14 and N15 are in the off-state. When the first input terminal in1(k) is at the L level and the second input terminal in2(k) is at the H level, the thin film transistors N14 and N15 are in the on-state and the thin film transistors N13 and N16 are in the off-state.
During the period when the node A is at the H level, the complementary capacitor C1 and the gate capacitor of the thin film transistor N11 are charged. Thus, if the clock signal ck is switched to the H level and Vdd appears at the output node out(k) in the period during which the node A is at the H level, the potential of the node A changes in such a manner as to be raised by the potential equal to the voltage charged in the complementary capacitor C1 and so on. At this time, a voltage equal to or higher than the threshold voltage Vth(N11) of the thin film transistor N11 is ensured as the gate-source voltage Vgs thereof due to bootstrap operation, and thus the waveform having the same amplitude as that of the clock signal ck appears at the output node out(k).
That is, the shift register circuit shown in FIG. 7 operates to extract the clock signal ck and output it from the output node sequentially from the first register stage. The periods indicated by shaded areas in the waveform diagrams of FIGS. 10D and 10E correspond to the periods during which the nodes A and B are in the floating state. The floating period of the node A is indispensable for the bootstrap operation.
Examples of documents about the related art include Japanese Patent Laid-open No. 2005-149624 and Japanese Patent Laid-open No. 2006-277789.